FIG. 1 illustrates a prior art memory system. As shown, a memory controller 110 outputs a pair of differential data signals DQ and DQN to a memory module 120; for example, during a write operation. The memory module 120 includes a plurality of memory devices 122. Each memory device 122 may receive a pair of differential data signals DQ and DQN through each of a plurality of data signal lines on the motherboard. More specifically, each memory device 122 includes an input circuit 124 for receiving the differential data signals DQ and DQN and outputting a data signal represented by the differential data signals DQ and DQN. A memory section 126 of the memory device 122 may store the data represented by the data signal.
While not shown, it will be appreciated that a memory device 122 may also output differential data signals to the memory controller 110; for example, during a read operation (e.g., reading data from a memory section 126 of a memory device 122). And, while not shown, the memory controller 110 also includes an input circuit for receiving the differential data signals and generating a data signal therefrom.
For the purposes of explanation only, operation of the input circuit 124 at a memory device 122 will be described; however, it will be understood that the same operation may occur at the memory controller 110.
FIG. 2 illustrates portions of the conventional memory system in greater detail. As shown, at the memory controller 110, a well-known differential driver 112 generates the pair of differential data signals DQ and DQN based on input data D and DN, where DN is a voltage representing the logical inverse of that represented by the voltage D.
The first differential data signal DQ travels to the input circuit 124 of a memory device 122 via a first path PATH1 and the second differential data signal DQN travels to the input circuit 124 via a second path PATH2. The input circuit 124 is a differential amplifier DA that differentially amplifies the differential data signals to generate a data signal DATA.
FIG. 3A illustrates a waveform diagram of ideally generated differential data signals for data alternating between logic high and logic low, and FIG. 3B illustrates a waveform of a data signal generated from the ideal differential data signals. As shown by FIG. 3A, the second differential data signal DQN is ideally the inverse of the first differential data signal DQ such that the first and second differential data signals DQ and DQN transition between the same low and high voltages. As such, the first and second differential data signals DQ and DQN form an eye pattern wherein (1) each eye representing a logic low data signal has height HI equal to the height H2 of each eye representing a logic high data signal and (2) each eye representing a logic low data signal has a time interval or width W1 equal to the width W2 of each eye representing a logic high data signal. As further shown in FIG. 3A, the DC voltage VDC1 of the first differential data signal DQ is the same as the DC voltage VDC2 of the second differential data signal DQN such that no offset between the DC voltages VDC1 and VDC2 exists.
Because of the ideal characteristics of the first and second differential data signals, the resulting data signal has an ideal duty ratio of 50% as shown in FIG. 3B. Namely, the logic high periods of the data signal have the same time length as the logic low periods of the data signal. It should be understood that in normal operation, the differential data signals may represent logic high for two or consecutive periods and may represent logic low for two or more consecutive periods; however, the lengths of a single logic high period and a single logic low period define the duty ratio.
Unfortunately, in practice, the voltage swings of the first and second differential data signals DQ and DQN are not necessarily the same. Due to imperfect manufacturing tolerances, chip mismatch and/or channel mismatch may cause the differential data signals DQ and DQN as received at the input circuit 124 to differ from the ideal.
FIG. 3C illustrates one example case of how the differential data signals DQ and DQN may differ from the ideal shown in FIG. 3A. As shown, the voltage swings of the differential data signals DQ and DQN differ such that (1) each eye representing a logic low data signal has height H1 that is less than the height H2 of each eye representing a logic high data signal and (2) each eye representing a logic low data signal has a time interval or width W1 that is less the width W2 of each eye representing a logic high data signal. As a result, the data signal, as shown in FIG. 3D, may be erroneously generated (e.g., logic low state may not be detected or timely detected), and the data signal will have a duty ratio greater 50%. In that case, the logic low data of the data signal DATA may not be written into the memory cell array of the memory device 122 due to the lack of set up and hold time of the logic low data. Indicative of these conditions, the DC voltage VDC1 of the first differential data signal is greater than the DC voltage VDC2 of the second differential data signal. Thus a DC offset voltage exists between the first and second differential data signals.
FIGS. 3E and 3F illustrate yet another example of non-ideal differential data signals and the resulting data signal. As in the example of FIGS. 3C and 3D, a positive DC offset voltage exists because VDC1 is greater than VDC2; however, it will be appreciated that numerous other example situations exist in which a negative DC offset voltage (i.e., where VDC1 is less than VDC2) occurs. When a negative DC offset voltage occurs, the duty ratio of the resulting data signal may be less than 50%.